The present invention generally relates to test methods for synthesized logic circuits, and more particularly, to a method for automatically inserting test logic into synthesized logic circuits.
In the past, it has been the general practice for engineers to manually add or insert test logic into synthesized logic circuits, such as an application specific integrated circuit (ASIC) generated using a logic synthesizer. However, if the structure of the logic circuit changed, the logic synthesizer would be used to generate new logic and the engineer would again manually reinsert test logic functions into the new logic circuit. Because many manufacturers of custom ASICs use their own unique methods testing, CAD tools normally do not automatically support fault grading or the creation of test insertion logic.
Therefore, it is an objective of the present invention to provide for a test logic insertion method for use in designing synthesized logic circuits.